ATmega165 datasheet(86/336 Pages) ATMEL

86 / 336 page

ATmega165/V

2573G–AVR–07/09

Note:

1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 def-

initions. However, the functionality and location of these bits are compatible with

previous versions of the timer.

• Bit 5:4 – COM0A1:0: Compare Match Output Mode

These bits control the Output Compare pin (OC0A) behavior. If one or both of the

COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the

I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit cor-

responding to the OC0A pin must be set in order to enable the output driver.

When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the

WGM01:0 bit setting. Table 43 shows the COM0A1:0 bit functionality when the

WGM01:0 bits are set to a normal or CTC mode (non-PWM).

Table 44 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast

PWM mode.

Note:

1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case,

the compare match is ignored, but the set or clear is done at TOP. See “Fast PWM

Mode” on page 81 for more details.

Table 42. Waveform Generation Mode Bit Description(1)

Mode

WGM01

(CTC0)

WGM00

(PWM0)

Timer/Counter

Mode of Operation

TOP

Update of

OCR0A at

TOV0 Flag

Set on

Normal

0xFF

Immediate

MAX

PWM, Phase Correct

0xFF

TOP

BOTTOM

CTC

OCR0A

Immediate

MAX

Fast PWM

0xFF

BOTTOM

MAX

Table 43. Compare Output Mode, non-PWM Mode

COM0A1

COM0A0

Description

Normal port operation, OC0A disconnected.

Toggle OC0A on compare match

Clear OC0A on compare match

Set OC0A on compare match

Table 44. Compare Output Mode, Fast PWM Mode(1)

COM0A1

COM0A0

Description

Normal port operation, OC0A disconnected.

Reserved

Clear OC0A on compare match, set OC0A at BOTTOM,

(non-inverting mode)

Set OC0A on compare match, clear OC0A at BOTTOM,

(inverting mode)

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