ATmega165 datasheet(6/336 Pages) ATMEL

6 / 336 page

ATmega165/V

2573G–AVR–07/09

tors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset

occurs.

Port F also serves the functions of the JTAG interface.

Port G (PG4..PG0)

Port G is a 5-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port G output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port G pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port G also serves the functions of various special features of the ATmega165 as listed

on page 66.

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will gener-

ate a reset, even if the clock is not running. The minimum pulse length is given in Table

16 on page 38. Shorter pulses are not guaranteed to generate a reset.

XTAL1

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting Oscillator amplifier.

AVCC

AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally

connected to V

CC, even if the ADC is not used. If the ADC is used, it should be con-

nected to V

CC through a low-pass filter.

AREF

This is the analog reference pin for the A/D Converter.

About Code

Examples

This documentation contains simple code examples that briefly show how to use various

parts of the device. Be aware that not all C compiler vendors include bit definitions in the

header files and interrupt handling in C is compiler dependent. Please confirm with the

C compiler documentation for more details.

These code examples assume that the part specific header file is included before com-

pilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC",

"CBI", and "SBI" instructions must be replaced with instructions that allow access to

extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and

"CBR".

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