ATmega165 datasheet(139/336 Pages) ATMEL

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139

ATmega165/V

2573G–AVR–07/09

Serial Peripheral

Interface – SPI

The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer

between the ATmega165 and peripheral devices or between several AVR devices. The

ATmega165 SPI includes the following features:

• Full-duplex, Three-wire Synchronous Data Transfer

• Master or Slave Operation

• LSB First or MSB First Data Transfer

• Seven Programmable Bit Rates

• End of Transmission Interrupt Flag

• Write Collision Flag Protection

• Wake-up from Idle Mode

• Double Speed (CK/2) Master SPI Mode

The PRSPI bit in “Power Reduction Register - PRR” on page 34 must be written to zero

to enable SPI module.

Figure 65. SPI Block Diagram

(1)

Note:

1. Refer to Figure 1 on page 2, and Table 27 on page 62 for SPI pin placement.

The interconnection between Master and Slave CPUs with SPI is shown in Figure 66.

The system consists of two shift Registers, and a Master clock generator. The SPI Mas-

ter initiates the communication cycle when pulling low the Slave Select SS pin of the

desired Slave. Master and Slave prepare the data to be sent in their respective shift

Registers, and the Master generates the required clock pulses on the SCK line to inter-

change data. Data is always shifted from Master to Slave on the Master Out – Slave In,

MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line. After

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ATmega165 데이터시트(PDF) 139 Page - ATMEL Corporation