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AT89LP4052 데이터시트(PDF) 73 Page - ATMEL Corporation

부품명 AT89LP4052
상세설명  8-bit Microcontroller with 2/4-Kbyte Flash
PDF  94 Pages
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제조업체  ATMEL [ATMEL Corporation]
홈페이지  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT89LP4052 데이터시트(HTML) 73 Page - ATMEL Corporation

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73
3547J–MICRO–10/09
AT89LP2052/LP4052
23.5
In-System Programming (ISP)
The AT89LP2052/LP4052 offers a serial programming interface which may be used in place of
the parallel programming interface or to program the device while in system. In this document
serial programming and In-System Programming (ISP) refer to the same interface. ISP supports
the same command set as parallel programming. However, during ISP command bytes are
entered serially over the Serial Peripheral Interface (SPI) pins. The device connections are
shown in Figure 23-21. The ISP Enable User Fuse must be enabled through Parallel Program-
ming prior to entering the first ISP session. ISP itself may disable the ISP Fuse, however any
changes to the ISP fuses will not take affect until the device has been powered down and up
again. The programmer must take care not to accidentally disable the ISP Fuse as this will make
the device unprogrammable through the serial interface. Only Parallel Programming may re-
enable the fuse.
Table 23-3.
Parallel Flash Programming and Verification Parameters
Symbol
Parameter
Min
Max
Units
V
PPH
Programming Enable Input High Voltage
11.5
12.5
V
VPPL
Programming Enable Input Low Voltage
-0.5
VCC
V
I
PP
Programming Enable Current
1.0
mA
tPWRUP
Power-on to RST High
10
µs
tPOR
Power-on Reset Time
2
ms
t
CSTP
CS Setup to V
PP High
10
µs
tHSTL
High Voltage Setting time
10
µs
tCLXH
CS Low to XTAL1 High
100
ns
t
XTH
XTAL1 High Width
125
ns
tXTL
XTAL1 Low Width
75
ns
tDSTP
Data Setup to XTAL1 High
50
ns
t
DHLD
Data Hold after XTAL1 High
50
ns
tXLDO
XTAL1 Low to Data Out
20
ns
tXLDV
XTAL1 Low to Data Valid
100
ns
t
XLCH
XTAL1 Low to CS High
100
ns
tCHDZ
CS High to Data Tri-state
20
ns
tCHBL
CS High to BUSY Low
3
µs
t
WRC
Write Cycle Time
4.5
ms
tERS
Erase Cycle Time
9
ms
t
BHPG
BUSY High to Next Erase/Write
3
µs
t
BHHl
BUSY High to V
PP Off
10
µs
tCLRL
CS Low to RST Low
1
µs
t
PWRDN
RST Low to Power Off
1
µs



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