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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ATtiny261-15MZ 데이터시트(PDF) 101 Page - ATMEL Corporation |
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ATtiny261-15MZ 데이터시트(HTML) 101 Page - ATMEL Corporation |
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101 / 227 page  101 7753C–AVR–07/09 ATtiny261/ATtiny461/ATtiny861 The design of the Output Compare Pin Configuration logic allows initialization of the OC1x state before the output is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of operation. For Output Compare Pin Configurations refer to Table 16-2 on page 103, Table 16-3 on page 105, Table 16-4 on page 107, and Table 16-5 on page 109. Figure 16-9. Compare Match Output Unit, Schematic PORTB0 DDRB0 DQ DDRB1 PORTB1 DQ DQ DQ clkI/O PORTB2 DDRB2 D Q DDRB3 PORTB3 D Q D Q D Q PORTB4 DDRB4 DQ DDRB5 PORTB5 DQ DQ DQ 1 0 1 0 OC1D PIN 2 1 0 Dead Time Generator D Q Q OCW1D clkTn OC1D PIN Output Compare Pin Configuration COM1D1:0 WGM11 OC1OE5:4 1 0 1 0 1 0 OC1B PIN 2 1 0 Dead Time Generator B Q Q OCW1B clkTn OC1B PIN Output Compare Pin Configuration COM1B1:0 WGM11 OC1OE3:2 1 0 1 0 OC1A PIN 0 1 Dead Time Generator A Q Q OCW1A clkTn OC1A PIN Output Compare Pin Configuration COM1A1:0 WGM11 OC1OE1:0 1 0 OC1A OC1A OC1B OC1B OC1D OC1D |
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