ATtiny24-20SSU datasheet(24/236 Pages) ATMEL

24 / 236 page

8006H–AVR–10/09

ATtiny24/44/84

Clock System

Figure 6-1 presents the principal clock systems in the AVR and their distribution. All of the clocks

need not be active at a given time. In order to reduce power consumption, the clocks to modules

not being used can be halted by using different sleep modes, as described in “Power Manage-

ment and Sleep Modes” on page 33.

Figure 6-1.

Clock Distribution

6.1

Clock Subsystems

The clock subsystems are detailed in the sections below.

6.1.1

CPU Clock – clk

CPU

The CPU clock is routed to parts of the system concerned with operation of the AVR core.

Examples of such modules are the General Purpose Register File, the Status Register and the

Data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing

general operations and calculations.

General I/O

Modules

CPU Core

RAM

clk

I/O

AVR Clock

Control Unit

clk

CPU

Flash and

EEPROM

clk

FLASH

Source clock

Watchdog Timer

Watchdog

Oscillator

Reset Logic

Clock

Multiplexer

Watchdog clock

Calibrated RC

Oscillator

Calibrated RC

Oscillator

External Clock

ADC

clk

ADC

Crystal

Oscillator

Low-Frequency

Crystal Oscillator

System Clock

Prescaler

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