ATmega325P datasheet(166/364 Pages) ATMEL

166 / 364 page

166

8023F–AVR–07/09

ATmega325P/3250P

xcki

Input from XCK pin (internal Signal). Used for synchronous slave

operation.

xcko

Clock output to XCK pin (Internal Signal). Used for synchronous master

operation.

fosc

XTAL pin frequency (System Clock).

18.3.1

Internal Clock Generation – The Baud Rate Generator

Internal clock generation is used for the asynchronous and the synchronous master modes of

operation. The description in this section refers to Figure 18-2 on page 165.

The USART Baud Rate Register (UBRRn) and the down-counter connected to it function as a

programmable prescaler or baud rate generator. The down-counter, running at system clock

osc), is loaded with the UBRRn value each time the counter has counted down to zero or when

the UBRRnL Register is written. A clock is generated each time the counter reaches zero. This

clock is the baud rate generator clock output (= f

osc/(UBRRn+1)). The Transmitter divides the

baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate generator out-

put is used directly by the Receiver’s clock and data recovery units. However, the recovery units

use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the

UMSELn, U2Xn and DDR_XCK bits.

Table 18-3 contains equations for calculating the baud rate (in bits per second) and for calculat-

ing the UBRRn value for each mode of operation using an internally generated clock source.

ATmega325P 데이터시트(PDF) 166 Page - ATMEL Corporation