ATtiny261A-MU datasheet(92/292 Pages) ATMEL

92 / 292 page

8197A–AVR–10/09

ATtiny261A/461A/861A

12.4.1

Counter Initialization for Asynchronous Mode

To set Timer/Counter1 to asynchronous mode follow the procedure below:

1. Enable PLL.

2. Wait 100 µs for PLL to stabilize.

3. Poll the PLOCK bit until it is set.

4. Set the PCKE bit in the PLLCSR register which enables the asynchronous mode.

12.5 Output Compare Unit

The comparator continuously compares TCNT1 with the Output Compare Registers (OCR1A,

OCR1B, OCR1C and OCR1D). Whenever TCNT1 equals to the Output Compare Register, the

comparator signals a match. A match will set the Output Compare Flag (OCF1A, OCF1B or

OCF1D) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output Com-

pare Flag generates an Output Compare interrupt. The Output Compare Flag is automatically

cleared when the interrupt is executed. Alternatively, the flag can be cleared by software by writ-

ing a logical one to its I/O bit location. The Waveform Generator uses the match signal to

generate an output according to operating mode set by bits PWM1A, PWM1B, WGM11:10 and

COM1x1:0. The top and bottom signals are used by the Waveform Generator for handling the

special cases of the extreme values in some modes of operation (See “Modes of Operation” on

page 97.). Figure 12-5 shows a block diagram of the Output Compare unit.

Figure 12-5. Output Compare Unit, Block Diagram

The OCR1x Registers are double buffered when using any of the Pulse Width Modulation

(PWM) modes. For the normal mode of operation, the double buffering is disabled. The double

buffering synchronizes the update of the OCR1x Compare Registers to either top or bottom of

the counting sequence. The synchronization prevents the occurrence of odd-length, non-sym-

OCFnx (Int.Req.)

= (10-bit Comparator )

8-BIT DATA BUS

TCNTn

WGM10

Waveform Generator

COMnX1:0

PWMnx

TCnH

OCWnx

10-BIT TCNTn

10-BIT OCRnx

OCRnx

FOCn

TOP

BOTTOM

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