 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
ST7585 데이터시트(PDF) 43 Page - Sitronix Technology Co., Ltd. |
|
|
|||||||||||||||||||||||||||||
ST7585 데이터시트(HTML) 43 Page - Sitronix Technology Co., Ltd. |
|
|
43 / 51 page  ST7585 Ver 1.0c 43/51 2009/04/14 SERIAL INTERFACE (3-Line Interface) First bit Last bit (VDD1 = 3.3V , Ta =25 ° C) Item Signal Symbol Condition Min. Max. Unit Serial clock period tSCYC 120 — SCLK “H” pulse width tSHW 60 — SCLK “L” pulse width SCLK tSLW 60 — Data setup time tSDS 20 — Data hold time SDA tSDH 10 — CSB-SCLK time tCSS 20 — CSB-SCLK time CSB tCSH 130 — ns (VDD1 = 2.8V , Ta =25 ° C) Item Signal Symbol Condition Min. Max. Unit Serial clock period tSCYC 180 — SCLK “H” pulse width tSHW 90 — SCLK “L” pulse width SCLK tSLW 90 — Data setup time tSDS 30 — Data hold time SDA tSDH 20 — CSB-SCLK time tCSS 30 — CSB-SCLK time CSB tCSH 160 — ns (VDD1 = 1.8V , Ta =25 ° C) Item Signal Symbol Condition Min. Max. Unit Serial clock period tSCYC 240 — SCLK “H” pulse width tSHW 120 — SCLK “L” pulse width SCLK tSLW 120 — Data setup time tSDS 60 — Data hold time SDA tSDH 50 — CSB-SCLK time tCSS 40 — CSB-SCLK time CSB tCSH 190 — ns *1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD1 as the standard. |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
