ST7713 datasheet(75/159 Pages) SITRONIX

75 / 159 page

ST7713

Ver 1.6

2008-05

9.11 Address Counter

The address counter sets the addresses of the display data RAM for writing and reading.

Data is written pixel-wise into the RAM matrix of DRIVER. The data for one pixel or two pixels is collected (RGB 6-6-6-bit),

according to the data formats. As soon as this pixel-data information is complete the “Write access” is activated on the RAM.

The locations of RAM are addressed by the address pointers. The address ranges are X=0 to X=131 (83h) and Y=0 to

Y=131 (83h). Addresses outside these ranges are not allowed. Before writing to the RAM, a window must be defined that

will be written. The window is programmable via the command registers XS, YS designating the start address and XE, YE

designating the end address.

For example the whole display contents will be written, the window is defined by the following values: XS=0 (0h) YS=0 (0h)

and XE=131 (83h), YE=131 (83h).

In vertical addressing mode (MV=1), the Y-address increments after each byte, after the last Y-address (Y=YE), Y wraps

around to YS and X increments to address the next column. In horizontal addressing mode (V=0), the X-address

increments after each byte, after the last X-address (X=XE), X wraps around to XS and Y increments to address the next

row. After the every last address (X=XE and Y=YE) the address pointers wrap around to address (X=XS and Y=YS).

For flexibility in handling a wide variety of display architectures, the commands “CASET, RASET” and ”MADCTL” (see

section 10 command list), define flags MX and MY, which allows mirroring of the X-address and Y-address. All

combinations of flags are allowed. Section 9.12 show the available combinations of writing to the display RAM. When MX,

MY and MV will be changed the data bust be rewritten to the display RAM.

For each image condition, the controls for the column and row counters apply as section 9.12 below:

Condition

Column Counter

Row Counter

When RAMWR/RAMRD command is accepted

Return to “Start

Column (XS)”

Return to “Start

Row (YS)”

Complete Pixel Read / Write action

Increment by 1

No change

The Column counter value is larger than “End Column (XE)”

Return to “Start

Column (XS)”

Increment by 1

The Column counter value is larger than “End Column (XE)” and

the Row counter value is larger than “End Row (YE)”

Return to “Start

Column (XS)”

Return to “Start

Row (YS)”

9.12. Memory Data Write/ Read Direction

The data is written in the order illustrated above. The Counter which dictates where in the physical memory the data is to be

written is controlled by “Memory Data Access Control” Command, bits B5 (MV), B6 (MX), B7 (MY) as described below.

Fig. 9.12.1 Data streaming order

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