| 전자부품 데이터시트 검색엔진 |
|
AS8500 데이터시트(PDF) 27 Page - ams AG |
|
|
|||||||||||||||||||||||||||||
AS8500 데이터시트(HTML) 27 Page - ams AG |
|
27 / 41 page ![]() AS8500 - Data Sheet austriamicrosystems Revision 1.2, 08-Junel-06 www.austriamicrosystems.com Page 27 of 41 The trailing edge of INTN signals the start of a new measurement. The determination of Tcnv and Tres from the parameter settings is: Tcnv % R1/(fovs*2) Tres = MM*Tcnv*R2*2 with R1=OSR and R2=number of averages 8.3 SDI bus operation SDI bus is a 2-line bi-directional interface between one master and one slave unit. Typically the master unit is a microcontroller with software- implemented SDI protocol. The ASSP is always the slave unit. SDI bus operation is presented on figure 6. During data transfers the sdat signal changes while sclk is low. The sdat signal can change while sclk is high only to generate start or exception conditions. Strobe ASSP The master unit always generates the sclk signal. The master unit generates the sdat signal in start, direction, address, master-write data and exception conditions. The master sdat pin is in high-impedance state in master-read data condition. INTN Tres Tcnv start measurement i i-1 i+1 i-2 i-1 i available results on SDI SDAT sclk Start Direction Data transfer Address Register data Exception Figure 5: INTN pin in modes 1 and 2 Figure 6: SDI bus operation |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |