STM32F100C4 datasheet(15/84 Pages) STMICROELECTRONICS

15 / 84 page

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Description

Doc ID 16455 Rev 2

15/84

2.6

Nested vectored interrupt controller (NVIC)

The STM32F100xx value line embeds a nested vectored interrupt controller able to handle

up to 41 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3)

and 16 priority levels.

●

Closely coupled NVIC gives low latency interrupt processing

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Interrupt entry vector table address passed directly to the core

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Closely coupled NVIC core interface

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Allows early processing of interrupts

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Processing of late arriving higher priority interrupts

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Support for tail-chaining

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Processor state automatically saved

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Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

2.7

External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 18 edge detector lines used to generate

interrupt/event requests. Each line can be independently configured to select the trigger

event (rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect an external line with a

pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected

to the 16 external interrupt lines.

2.8

Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is

selected as default CPU clock on reset. An external 4-24 MHz clock can be selected, in

which case it is monitored for failure. If failure is detected, the system automatically switches

back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full

interrupt management of the PLL clock entry is available when necessary (for example on

failure of an indirectly used external crystal, resonator or oscillator).

Several prescalers allow the configuration of the AHB frequency, the high-speed APB

(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and

the APB domains is 24 MHz.

2.9

Boot modes

At startup, boot pins are used to select one of three boot options:

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Boot from user Flash

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Boot from system memory

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Boot from embedded SRAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by

using USART1. For further details please refer to AN2606.

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