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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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VG37648041AT 데이터시트(PDF) 83 Page - Vanguard International Semiconductor |
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VG37648041AT 데이터시트(HTML) 83 Page - Vanguard International Semiconductor |
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83 / 86 page  Document : 1G5-0157 Rev.1 Page 83 VIS Preliminary VG37648041AT 256M:x4, x8, x16 CMOS Synchronous Dynamic RAM tIS DI n=Data In for column n Burst Length=4 in the case shown 3 subsequent elements of Data In are provided in the programmed order following DI n DIS AP=Disable Autoprecharge *=”Don’t Care”, if A10 is HIGH at this point PRE=PRECHARGE, ACT=ACTIVE, RA=Row Address, BA=Bank Address NOP commands are shown for ease of illustration; other commands may be possible at these times tIH tIS tIH tCK tCH tCL NOP WRITE NOP NOP NOP NOP PRE NOP NOP ACT DON’T CARE UNDEFINED CLK# CLK CKE COMMAND A10 DQS x4:A0,A9,A11 DQ DM WRITE-WITHOUT AUTO PRECHARGE tIS tIH Col n x8:A0,A9 x16:A0,A8 x4:A12 x8:A9,A12 x16:A8,A9,A12 BA0,BA1 tIS tIH Bank x *Bank x RA RA ONE BANK DIS AP tIS tIH tIH ALL BANKS RA BA tWCP tDSL tWPR tDSS tDSH tWPO tWR tRP Dl n VALID |
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