ICS9220B datasheet(5/16 Pages) IDT

5 / 16 page

1427A—01/26/10

ICS9220B

Programmable Rambus

TM XDRTMClock Generator

IDTTM

Programmable RambusTM XDRTMClock Generator

2C Table: Frequency Control Register

Pin #

Name

Control Function

Type

PWD

Bit 7

Reserved

Bit 6

Reserved

Bit 5

Reserved

Bit 4

Reserved

Bit 3

Reserved

Bit 2

Reserved

Bit 1

Reserved

Bit 0

Reserved

2C Table: VCO Frequency Control Register

Pin #

Name

Control Function

Type

PWD

Bit 7

Reserved

Bit 6

Reserved

Bit 5

Reserved

Bit 4

Reserved

Bit 3

M DIV3

Bit 2

M DIV2

Bit 1

M DIV1

Bit 0

M DIV0

2C Table: VCO Frequency Control Register

Pin #

Name

Control Function

Type

PWD

Bit 7

Reserved

Bit 6

Reserved

Bit 5

N DIV5

Bit 4

N DIV4

Bit 3

N DIV3

Bit 2

N DIV2

Bit 1

N DIV1

Bit 0

N DIV0

The decimal representation of

M and N Divider in Byte 5 and

6 will configure the PLL VCO

frequency. VCO frequency =

100 x

{[NDIV(5:0)+2]/[MDIV(3:0)+2]}

Byte 5

Byte 4

Byte 6

N Divider Programming

b(5:0)

M Divider Programming

b(3:0)

The decimal representation of

M and N Divider in Byte 5 and

6 will configure the PLL VCO

frequency. VCO frequency =

100 x

{[NDIV(5:0)+2]/[MDIV(3:0)+2]}

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