| 전자부품 데이터시트 검색엔진 |
|
ICS9220B 데이터시트(PDF) 9 Page - Integrated Device Technology |
|
|
|||||||||||||||||||||||||||||
ICS9220B 데이터시트(HTML) 9 Page - Integrated Device Technology |
|
9 / 16 page ![]() 1427A—01/26/10 ICS9220B Programmable Rambus TM XDRTMClock Generator 9 IDTTM Programmable RambusTM XDRTMClock Generator Absolute Maximum Ratings Supply Voltage 4.0 V Logic Inputs GND –0.5 V to VDD +0.5 V Ambient Operating Temperature -40°C to +85°C Storage Temperature –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. DC Characteristics - Outputs TA = -40°C to +85°C; Supply Voltage AVDD2.5, VDD2.5 = 2.5 V +/- 5% (unless otherwise stated) SYMBOL CONDITIONS MIN TYP MAX UNITS tPU Power within spec to outputs within spec 3ms tCO SMBus or Mode Select transition to outputs valid and within spec 3ms VOX Measured as shown in Fig. 3 0.9 1.1 V VCOS Measured as shown in Fig. 3. Excludes over and undershoot. 300 350 mV VOL, ABS Measured at ODCLK_T/C pins 0.85 V VISET VDD = 2.3V, VOUT = 1V 0.98 1.02 V IOL/IREF IREF is equal to VISET/RRC. Tolerance of RRC <=+/-1%. 6.8 7 7.2 - IOL, ABS Measured at ODCLK_T/C pins with termination per Figure 3. 45 - mA VOLSMB IOL = 4 mA -0.4 V IOLSMB VOL= 0.8 V 6- mA IOZ Differential clock output pins - 50 µΑ Notes: 1 There is no output latency or glitches if a value written to an output register is the same as its current contents. Minimum current at VOLABS Output Voltage Swing (peak-to-peak singled ended) Absolute output low voltage Reference Voltage for swing control current Ratio of output low current to reference current at typical VDD2.5 Low-level output voltage SMBus Low-level output current SMBus Tristate output current PARAMETER Power up latency State transition latency 1 Differential output crossing voltage |
|
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |