WM2625ID datasheet(4/9 Pages) WOLFSON

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WM2625

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 April 2001

Notes:

Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the

effects of zero code and full scale errors).

Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two

codes. A guarantee of monotonicity means the output voltage always changes in the same direction (or remains constant) as

the digital input code.

Zero code error is the voltage output when the DAC input code is zero.

Gain error is the deviation from the ideal full-scale output excluding the effects of zero code error.

Power supply rejection ratio is measured by varying VDD from 4.5V to 5.5V and measuring the proportion of this signal

imposed on the zero code error and the gain error.

Zero code error and Gain error temperature coefficients are normalised to full-scale voltage.

Output load regulation is the difference between the output voltage at full scale with a 10k

Ω load and 2kΩ load. It is

expressed as a percentage of the full scale output voltage with a 10k

Ω load.

IDD is measured while continuously writing code 128 to the DAC. For VIH < VDD - 0.7V and VIL > 0.7V supply current will

increase.

Slew rate results are for the lower value of the rising and falling edge slew rates

10. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling

edges. Limits are ensured by design and characterisation, but are not production tested.

11. SNR, SNRD, THD and SPFDR are measured on a synthesised sine wave at frequency fOUT generated with a sampling

frequency fs.

SERIAL INTERFACE

NCS

SCLK

DIN

5 15

D12

D13

D14

D15

SUD

SUCSCK

SUC16CS

Figure 1 Timing Diagram

Test Conditions:

RL = 10k

Ω, CL = 100pF. VDD = 5V

± 10%, V

REF = 2.048V and VDD = 3V

± 10%, V

REF = 1.024V over recommended operating

free-air temperature range (unless noted otherwise).

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tSUCSCK

Setup time, NCS low before first falling SCLK edge

tSUC16CS

Setup time, 16

th falling SCLK edge (when data bit D0

is sampled) before NCS rising edge.

tWH

Pulse duration, SCLK high.

tWL

Pulse duration, SCLK low.

tSUD

Setup time, data ready before SCLK falling edge.

tHD

Hold time, data held valid after SCLK falling edge.

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