WM2625

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 April 2001

6

DEVICE DESCRIPTION

GENERAL FUNCTION

The WM2625 is a dual 8-bit, voltage output DAC operating from a single supply. It uses a resistor

string network buffered with an op amp to convert 8-bit digital data to analogue voltage levels (see

Block Diagram). The output voltage is determined by the reference input voltage and the input code

according to the following relationship:

()

256

2

CODE

V

out

V

REFIN

=

INPUT

OUTPUT

1111

1111

()

256

255

2

REF

V

::

1000

0001

()

256

129

2

REF

V

1000

0000

()

REF

REF

V

V

=

256

128

2

0111

1111

()

256

127

2

REF

V

::

0000

0001

()

256

1

2

REF

V

0000

0000

0V

POWER ON RESET

An internal power-on-reset circuit resets the DAC register to all 0s on power-up.

BUFFER AMPLIFIER

The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a

2k

Ω load with a 100pF load capacitance.

EXTERNAL REFERENCE

The reference voltage input is buffered which makes the DAC input resistance independent of

code. The REF pin has an input resistance of 10M

Ω and an input capacitance of typically 5pF. The

reference voltage determines the DAC full-scale output.

SERIAL INTERFACE

Before writing any data to the WM2625, the interface must be enabled by setting NCS to low.

Incoming data on DIN (starting with the MSB) is then shifted bit-per-bit into the internal register on

the falling edges of SCLK. From there data is loaded into the target latch after 16 bits have been

transferred, or when NCS rises. Three internal latches can be addressed: DAC A, DAC B, or the

buffer latch. This makes it possible to update both DACs simultaneously or to update one

independently of the other (see ‘Addressing the Buffer and DAC Latches’, below).

SERIAL CLOCK AND UPDATE RATE

Figure 1 shows the device timing. The maximum serial rate is:

MHz

t

t

f

WL

WH

SCLK

20

1

min

min

max

=

+

=