WM2626

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 April 2001

4

Test Conditions:

air temperature range (unless noted otherwise).

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Reference Output (Internal reference)

Low reference voltage

1.003

1.024

1.045

V

High reference voltage

2.027

2.048

2.069

V

Output Current

±1

mA

Load capacitance

100

pF

Reference Input (External reference)

Reference input resistance

10

M

Ω

Reference input capacitance

5pF

Reference feedthrough

+ 1.024V dc, DAC code 0

-80

dB

Reference input bandwidth

DAC code 128

Slow

Fast

0.525

1.3

MHz

MHz

Digital Inputs

High level input current

Input voltage = VDD

1

µA

Low level input current

Input voltage = 0V

-1

µA

Input capacitance

8pF

Notes:

1.

Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the

effects of zero code and full scale errors).

2.

Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two

codes. A guarantee of monotonicity means the output voltage always changes in the same direction (or remains constant) as

the digital input code.

3.

Zero code error is the voltage output when the DAC input code is zero.

4.

Gain error is the deviation from the ideal full-scale output excluding the effects of zero code error.

5.

Power supply rejection ratio is measured by varying VDD from 4.5V to 5.5V and measuring the proportion of this signal

imposed on the zero code error and the gain error.

6.

Zero code error and Gain error temperature coefficients are normalised to full-scale voltage.

7.

Output load regulation is the difference between the output voltage at full scale with a 10k

Ω load and 2kΩ load. It is

expressed as a percentage of the full scale output voltage with a 10k

Ω load.

8.

increase.

9.

Slew rate is for an output change from 10% to 90% of full-scale output voltage, or vice versa. The results are for the lower

value of the rising and falling edge slew rates.

10. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling

edges. Limits are ensured by design and characterisation, but are not production tested.