X24C01A

1

DESCRIPTION

internally organized 128 x 8. The X24C01A features a

serial interface and software protocol allowing operation

on a simple two wire bus. Three address inputs allow up

to eight devices to share a common two wire bus.

tions requiring extended endurance. Inherent data re-

tention is greater than 100 years. Available in an eight

pin DIP and SOIC package.

FEATURES

—Active Current Less Than 1 mA

—Standby Current Less Than 50

—Typical Write Cycle Time of 5 ms

—Bidirectional Data Transfer Protocol

—Minimizes Total Write Time Per Byte

—Endurance: 100,000 Cycles

—Data Retention: 100 Years

© Xicor, 1991 Patents Pending

Characteristics subject to change without notice

1K

X24C01A

128 x 8 Bit

Preliminary Information

FUNCTIONAL DIAGRAM

3841 FHD F01

START

STOP

LOGIC

CONTROL

LOGIC

SLAVE ADDRESS

REGISTER

+COMPARATOR

H.V. GENERATION

TIMING

& CONTROL

WORD

ADDRESS

COUNTER

XDEC

YDEC

DOUT

ACK

32x32

DATA REGISTER

START CYCLE

(8) VCC

R/W

PIN

(4) VSS

(5) SDA

(6) SCL

(3) A2

(2) A1

(1) A0

DOUT

LOAD

INC

CK

8

(7) WC

3841-1