X24C01A

10

WRITE CYCLE LIMITS

Symbol

Parameter

Min.

Max.

Units

Write Cycle Time

5

10

ms

3841 PGM T10

The write cycle time is the time from a valid stop

condition of a write sequence to the end of the internal

erase/program cycle. During the write cycle, the X24C01A

bus interface circuits are disabled, SDA is allowed to

remain high, and the device does not respond to its slave

address.

Write Cycle Timing

SDA

8th BIT

WORD n

ACK

tWR

STOP

CONDITION

START

CONDITION

X24C01A

ADDRESS

SCL

3841 FHD F04

Guidelines for Calculating Typical Values of Bus

Pull-Up Resistors

SYMBOL TABLE

Must be

steady

Will be

steady

May change

from Low to

High

Will change

from Low to

High

May change

from High to

Low

Will change

from High to

Low

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

N/A

Center Line

is High

Impedance

OUTPUTS

INPUTS

WAVEFORM

3841 FHD F16

120

100

80

40

60

20

20

40

60

80 100 120

0

0

BUS CAPACITANCE (pF)

MIN.

RESISTANCE

MAX.

RESISTANCE

RMAX =

CBUS

tR

RMIN =

IOL MIN

VCC MAX

=1.8K

Ω

device requires to perform the internal write operation.