ADA4320-1

Rev. 0 | Page 5 of 16

TIMING REQUIREMENTS

Table 3.

Parameter

Min

Typ

Max

Unit

16

ns

32

ns

5

ns

16

ns

5

ns

3

ns

Input 10% to 90% Rise and Fall Times, SDATA, DATEN, Clock

10

ns

VALID DATA-WORD G1

MSB...LSB

VALID DATA-WORD G2

SDATA

CLK

TXEN

ANALOG

OUTPUT

DATEN

8 CLOCK CYCLES

GAIN TRANSFER (G1)

GAIN TRANSFER (G2)

SIGNAL AMPLITUDE (p-p)

Figure 2. Serial Interface Timing

SDATA MSB

MSB – 1

MSB – 2

CLK

VALID DATA BIT

Figure 3. SDATA Timing