ADA4320-1

Rev. 0 | Page 7 of 16

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

19

18

17

16

15

14

1

2

3

4

5

6

7

GND

GND

VCC

VCC

VCC

RAMP

TXEN

13

GND

GND

GND

SLEEP

CLK

SDATA

DATEN

ADA4320-1

TOP VIEW

(Not to Scale

NOTES

1. EXPOSED THERMAL PAD MUST BE ELECTRICALLY AND

THERMALLY CONNECTED TO PCB GROUND (GND) PLANE.

Figure 4. Pin Configuration, Top View

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 2, 8, 9, 12,

17, 18, 19,

EPAD

GND

Common External Ground Reference.

3, 4, 5

VCC

Common Positive External Supply Voltage.

6

RAMP

External RAMP Capacitor (Optional).

7

TXEN

Transmit Enable. Logic 0 disables forward transmission, and Logic 1 enables forward transmission.

10

VIN−

11

VIN+

13

DATEN

Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0-to-1 transition

transfers the latched data to the attenuator core (updates the gain) and simultaneously inhibits serial data transfer

into the register. A 1-to-0 transition inhibits the data latch (holds the previous, and simultaneously enables the

register for serial data load).

14

SDATA

Serial Data Input. This digital input allows an 8-bit serial control word to be loaded into the internal register with the

most significant bit (MSB) first.

15

CLK

Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-slave shift register. A

Logic 0-to-1 transition latches the data bit, and a Logic 1-to-0 transition transfers the data bit to the slave. This

requires the input serial data-word to be valid at or before this clock transition.

16

SLEEP

Low Power Sleep Mode. In sleep mode, the supply current is reduced to 12 μA typical. Logic 0 powers down

the device, and Logic 1 powers up the device.

20, 22

VOUT−

21, 23

VOUT+

24

COMP

Internal Compensation. This pin must be externally decoupled (0.1 μF capacitor).