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74LVC2G53GD 데이터시트(PDF) 12 Page - NXP Semiconductors |
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74LVC2G53GD 데이터시트(HTML) 12 Page - NXP Semiconductors |
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12 / 23 page ![]() 74LVC2G53_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 18 June 2008 12 of 23 NXP Semiconductors 74LVC2G53 2-channel analog multiplexer/demultiplexer 11.1 Waveforms and test circuits Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 16. Input (Yn or Z) to output (Z or Yn) propagation delays tPLH tPHL VM VM VM VM GND VI VOH VOL Yn or Z input Z or Yn output 001aac361 Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 17. Enable and disable times VM VI GND VCC VOL VOH GND S, E input output LOW to OFF OFF to LOW output HIGH to OFF OFF to HIGH VM 001aad393 VM tPZL tPHZ tPZH VX VY switch disabled switch enabled switch enabled Z, Yn Z, Yn tPLZ Table 10. Measurement points Supply voltage Input Output VCC VM VM VX VY 1.65 V to 2.7 V 0.5VCC 0.5VCC VOL + 0.15 V VOH − 0.15 V 2.7 V to 5.5 V 0.5VCC 0.5VCC VOL + 0.3 V VOH − 0.3 V |
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