전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

CS4294/CS4298 데이터시트(PDF) 15 Page - Cirrus Logic

부품명 CS4294/CS4298
상세설명  Audio Codec ??7 with Headphone Amplifier
PDF  66 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS4294/CS4298 데이터시트(HTML) 15 Page - Cirrus Logic

Back Button CS4294/CS4298 Datasheet HTML 11Page - Cirrus Logic CS4294/CS4298 Datasheet HTML 12Page - Cirrus Logic CS4294/CS4298 Datasheet HTML 13Page - Cirrus Logic CS4294/CS4298 Datasheet HTML 14Page - Cirrus Logic CS4294/CS4298 Datasheet HTML 15Page - Cirrus Logic CS4294/CS4298 Datasheet HTML 16Page - Cirrus Logic CS4294/CS4298 Datasheet HTML 17Page - Cirrus Logic CS4294/CS4298 Datasheet HTML 18Page - Cirrus Logic CS4294/CS4298 Datasheet HTML 19Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 15 / 66 page
background image
CS4202
DS549PP2
15
3. AC-LINK FRAME DEFINITION
The AC-link is a bi-directional serial port with data
organized into frames consisting of one 16-bit and
twelve 20-bit time-division multiplexed slots.
Slot 0 is a special reserved time slot containing
16-bits which are used for AC-link protocol infra-
structure. Slots 1 through 12 contain audio or con-
trol/status data. Both the serial data output and
input frames are defined from the controller per-
spective, not from the CS4202 perspective.
The controller synchronizes the beginning of a
frame with the assertion of the SYNC signal.
Figure 9 shows the position of each bit location
within the frame. The first bit position in a new se-
rial data frame is F0 and the last bit position in the
serial data frame is F255. When SYNC goes active
(high) and is sampled active by the CS4202 (on the
falling edge of BIT_CLK), both devices are syn-
chronized to a new serial data frame. The data on
the SDATA_OUT pin at this clock edge is the final
bit of the previous frame’s serial data. On the next
rising edge of BIT_CLK, the first bit of Slot 0 is
driven by the controller on the SDATA_OUT pin.
On the next falling edge of BIT_CLK, the CS4202
latches this data in as the first bit of the frame.
20.8
µs
(48 kHz)
Tag Phase
Data Phase
12.288 MHz
81.4 ns
SYNC
BIT_CLK
SDATA_OUT
SDATA_IN
F0
F1
F2
F16
F15
F14
F13
F12
F35
F56
F76
D19
F255
Valid
Frame
Slot 1
Valid
0
R/W
0
WD15
F36
F57
D19
D18
D19
D19
D18
D19
RD15
0
0
0
0
F0
F1
F2
F16
F15
F14
F13
F12
F35
F56
F76
F255
F36
F57
F255
F255
0
0
GPIO
INT
F96
F96
D19
Slot 0
Slot 1
Slot 2
Slot 3
Slot 4
Slots 5-12
Slot 2
Valid
Slot 1
Valid
Slot 2
Valid
Codec
Ready
0
Slot 12
Valid
Codec
ID1
Codec
ID0
Slot 12
Valid
GPIO
INT
Bit Frame Position:
Bit Frame Position:
Figure 9. AC-link Input and Output Framing



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com