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CS8415A-CSZ 데이터시트(PDF) 45 Page - Cirrus Logic

부품명 CS8415A-CSZ
상세설명  96 kHz Digital Audio Interface Receiver
PDF  46 Pages
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS8415A-CSZ 데이터시트(HTML) 45 Page - Cirrus Logic

Back Button CS8415A-CSZ Datasheet HTML 38Page - Cirrus Logic CS8415A-CSZ Datasheet HTML 39Page - Cirrus Logic CS8415A-CSZ Datasheet HTML 40Page - Cirrus Logic CS8415A-CSZ Datasheet HTML 41Page - Cirrus Logic CS8415A-CSZ Datasheet HTML 42Page - Cirrus Logic CS8415A-CSZ Datasheet HTML 43Page - Cirrus Logic CS8415A-CSZ Datasheet HTML 44Page - Cirrus Logic CS8415A-CSZ Datasheet HTML 45Page - Cirrus Logic CS8415A-CSZ Datasheet HTML 46Page - Cirrus Logic  
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DS470F4
45
CS8415A
15.3.4
Jitter Attenuation
Shown in Figure 21, Figure 22, Figure 23, and Figure 24 are jitter attenuation plots for the various revi-
sions of the CS8415A when used with the appropriate external PLL component values (as noted in
Table 6). The AES3 and IEC60958-4 specifications do not have allowances for locking to sample rates
less than 32 kHz. These specifications state a maximum of 2 dB jitter gain or peaking.
10
−1
10
0
10
1
10
2
10
3
10
4
10
5
−20
−15
−10
−5
0
5
Jitter Frequency (Hz)
10
−1
10
0
10
1
10
2
10
3
10
4
10
5
−20
−15
−10
−5
0
5
Jitter Frequency (Hz)
10
−1
10
0
10
1
10
2
10
3
10
4
10
5
−25
−20
−15
−10
−5
0
5
Jitter Frequency (Hz)
10
−1
10
0
10
1
10
2
10
3
10
4
10
5
−25
−20
−15
−10
−5
0
5
Jitter Frequency (Hz)
Figure 21. Revision A
Figure 22. Revision A1
Figure 23. Revision A2 using A1 Values
Figure 24. Revision A2 using A2* Values



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