XIO2001 datasheet(72/128 Pages) TI

72 / 128 page

XIO2001

SCPS212D – MAY 2009 – REVISED JANUARY 2010

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4.60 GPIO Data Register

This register reads the state of the input mode GPIO terminals and changes the state of the output mode

GPIO terminals. Writing to a bit that is in input mode or is enabled for a secondary function is ignored. The

secondary functions share GPIO0 (CLKRUN), GPIO1 (PWR_OVRD), GPIO3 (SDA), and GPIO4 (SCL).

The default value at power up depends on the state of the GPIO terminals as they default to

general-purpose inputs. See Table 4-34 for a complete description of the register contents.

PCI register offset:

B6h

Read-only, Read/Write

Default value:

00XXh

BIT NUMBER

RESET STATE

Table 4-34. GPIO Data Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:5

RSVD

Reserved. Returns 000h when read.

4(1)

GPIO4_DATA

GPIO 4 data. This bit reads the state of GPIO4 when in input mode or changes the state of

GPIO4 when in output mode.

3(1)

GPIO3_DATA

GPIO 3 data. This bit reads the state of GPIO3 when in input mode or changes the state of

GPIO3 when in output mode.

2(1)

GPIO2_DATA

GPIO 2 data. This bit reads the state of GPIO2 when in input mode or changes the state of

GPIO2 when in output mode.

1 (1)

GPIO1_DATA

GPIO 1 data. This bit reads the state of GPIO1 when in input mode or changes the state of

GPIO1 when in output mode.

0(1)

GPIO0_DATA

GPIO 0 data. This bit reads the state of GPIO0 when in input mode or changes the state of

GPIO0 when in output mode.

(1)

These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

4.61 TL Control and Diagnostic Register 0

The contents of this register are used for monitoring status and controlling behavior of the bridge. See

Table 4-35 for a complete description of the register contents. It is recommended that all values within this

interoperability or other problems.

PCI register offset:

C0h

Read/Write

Default value:

0000 0001h

BIT NUMBER

RESET STATE

BIT NUMBER

RESET STATE

Table 4-35. Control and Diagnostic Register 0 Description

ACCES

BIT

FIELD NAME

DESCRIPTION

31:24(1)

PRI_BUS_NUM

This field contains the captured primary bus number.

23:19(1)

PRI_DEVICE_ NUM

This field contains the captured primary device number.

(1)

These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

Classic PCI Configuration Space

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