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10HSI-S008-R0-C 데이터시트(PDF) 48 Page - Hirose Electric |
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10HSI-S008-R0-C 데이터시트(HTML) 48 Page - Hirose Electric |
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48 / 71 page ![]() Signal Integrity Report – IT3 (32mm) Page 48 Figure 76 Power Sum of FEXT for port 15 of connector only 4.1.2 S parameters (vias only) Figure 77 shows the single-ended via model S-parameters of port 15, as described in Section 3.1.2. Figure 77 S-parameters for port 15 of via transition with routing on layer 16 4.1.3 S parameters (vias + connector + vias) Figure 78 shows the S-parameters (i.e., insertion loss, return loss, NEXT, and FEXT) for port 15 of the cascaded vias/connector/vias model with PCB routing in the 16th layer for both via |
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