10HSI-S008-R0-C datasheet(16/71 Pages) HIROSE

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Signal Integrity Report – IT3 (32mm)

Page 16

to a short via stub (Note that in IT3_demo_board_v2.doc, a larger routing layer corresponds to a

longer via-stub).

The via transition through the middle layer 16 of the PCB was studied in order to test a

relatively long via stub of ~60mil. Figure 25 shows the top and side views of the transition which

includes the PCB layers of the traces connected to each via. Via models through layers 3, layer 12,

layer 16, layer 19, and layer 28 have been modeled to study the effects of the insertion loss for short

and long via stubs. Only three routing layers are needed to route all differential pairs on the IT3

connector (with two pairs exiting on one side and three on the other side of the connector, as

observed in Figure 25)

The ports have been numbered such that 1 to 30 correspond to the top side of the PCB, and 31

to 60 are for the PCB trace connections. Ports 1-2 are grouped into pair 1, and ports 3-4 are grouped

into pair 2, etc.

Figure 26 shows the corresponding SDD for pair 8 (or ports 15-16) of via transition with PCB

routing on layer 16.

Layer No.

Mil

Solder mask

0.5

TOP

2.84

Pre-preg

4.5

Ground

0.7

Core

Sig 1

0.7

Pre-preg

3.5

Sig 2

0.7

Core

Ground

0.7

Pre-preg

3.5

Ground

0.7

Core

Sig 3

0.7

Pre-preg

3.5

Sig 4

0.7

Core

Ground

0.7

Pre-preg

3.5

Ground

0.7

Core

Sig 5

0.7

Pre-preg

3.5

Sig 6

0.7

Core

Ground

0.7

Pre-preg

3.5

Ground

0.7

Core

Sig 7

0.7

Pre-preg

3.5

10HSI-S008-R0-C 데이터시트(PDF) 16 Page - Hirose Electric

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