PCA9541ADSLASH01 datasheet(9/41 Pages) NXP

9 / 41 page

PCA9541A_3

Product data sheet

Rev. 03 — 16 July 2009

9 of 41

NXP Semiconductors

PCA9541A

2-to-1 I2C-bus master selector with interrupt logic and reset

• If a master was connected to the downstream bus prior to the disconnect, then an

interrupt is sent on the respective interrupt output in an attempt to let that master

know that it is no longer connected to the downstream bus. This is indicated by setting

the BUSLOST bit in the Interrupt Status Register.

• If the combination of the BUSON and the NBUSON bits causes a master to be

connected to the downstream bus and if there is no change in the BUSON bits since

when the disconnect took effect, then the master requesting the bus is connected to

the downstream bus. If it requests a bus initialization sequence, then it is performed.

• If there is no change in the combination of the BUSON and the NBUSON bits and a

new master wants the bus, then the downstream bus is disconnected from the old

master that was using it and the new master gets control of it. Again, the bus

initialization if requested is done. The appropriate interrupt signals are generated.

After a master has sent the bus control request:

1. The previous master is disconnected from the I2C-bus. An interrupt to the previous

master is sent through its INT line to let it know that it lost control of the bus.

BUSLOST bit in the Interrupt Status Register is set. This interrupt can be masked by

setting the BUSLOSTMSK bit to logic 1.

2. A built-in bus initialization/recovery function can take temporary control of the

downstream channel to initialize the bus before making the actual switch to the new

bus master. This function is activated by setting the BUSINIT to logic 1 by the master

during the same write sequence as the one programming MYBUS and BUSON bits.

When activated and whether the bus was previously idle or not:

a. 9 clock pulses are sent on the SCL_SLAVE.

b. SDA_SLAVE line is released (HIGH) when the clock pulses are sent to

SCL_SLAVE. This is equivalent to sending 8 data bits and a not acknowledge.

c. Finally a STOP condition is sent to the downstream slave channel.

This sequence will complete any read transaction which was previously in process

and the downstream slave conﬁgured as a slave-transmitter should release the SDA

line because the PCA9541A did not acknowledge the last byte.

3. When the initialization has been requested and completed, the PCA9541A sends an

interrupt to the new master through its INT line and connects the new master to the

downstream channel. BUSINIT bit in the Interrupt Status Register is set. The switch

operation occurs after the master asking the bus control has sent a STOP

command. This interrupt can be masked by setting the BUSINITMSK bit to logic 1.

4. When the bus initialization/recovery function has not been requested (BUSINIT = 0),

the PCA9541A connects the new master to the slave downstream channel. The

switch operation occurs after the master asking the bus control has sent a

STOP command. PCA9541A sends an interrupt to the new master through its INT

line if the built-in bus sensor function detects a non-idle condition in the downstream

slave channel at the switching time. BUSOK bit in the Interrupt Status Register is set.

This means that a STOP condition has not been detected in the previous bus

communication and that an external bus recovery/initialization must be performed. If

an idle condition has been detected at the switching time, no interrupt will be sent.

This interrupt can be masked by setting the BUSOKMSK bit to logic 1.

Interrupt status can be read. See Section 8.4 “Interrupt Status registers” for more

information.

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