PCA9541APWSLASH03 datasheet(13/41 Pages) NXP

13 / 41 page

PCA9541A_3

Product data sheet

Rev. 03 — 16 July 2009

13 of 41

NXP Semiconductors

PCA9541A

2-to-1 I2C-bus master selector with interrupt logic and reset

Table 12 describes which command needs to be written to the Control Register when a

master device wants to take control of the I2C-bus. Byte written to the Control Register is a

function of the current I2C-bus control status performed after an initial reading of the

Control Register.

Current status of the I2C-bus is determined by the bits MYBUS, NMYBUS, BUSON and

NBUSON is one of the following:

• The master reading its Control Register does not have control and the I2C-bus is off.

• The master reading its Control Register does not have control and the I2C-bus is on.

• The master reading its Control Register has control and the I2C-bus is off.

• The master reading its Control Register has control and the I2C-bus is on.

‘I2C-bus off’ means that upstream and downstream channels are not connected together.

‘I2C-bus on’ means that upstream and downstream channels are connected together.

Remark: Only the 4 LSBs of the Control Register are described in Table 12 since only

those bits control the I2C-bus control. The logic value for the 4 MSBs is speciﬁc to the

application and are not discussed in the table.

The read sequence is performed by the master as:

S - 111xxxx0 - 000x0001 - Sr - 111xxxx1 - DataRead - P

The write sequence is performed by the master as:

S - 111xxxx0 - 000x0001 - DataWritten - P

Table 11.

Default Control Register values

Type version

Master

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

NTESTON TESTON

not used

BUSINIT

NBUSON

BUSON

NMYBUS

MYBUS

PCA9541A/01 MST_0

MST_1

PCA9541A/03 MST_0

MST_1

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