PCF2113AUSLASH10SLASHF4 datasheet(37/65 Pages) NXP

37 / 65 page

PCF2113_FAM_4

Product data sheet

Rev. 04 — 4 March 2008

37 of 65

NXP Semiconductors

PCF2113x

LCD controllers/drivers

11.2 I2C-bus interface

The I2C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are the Serial Data line (SDA) and the Serial Clock Line (SCL). Both lines

must be connected to a positive supply via pull-up resistors. Data transfer may be initiated

only when the bus is not busy.

Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH

level signal put on the bus by the transmitter during which time the master generates an

extra acknowledge related clock pulse. A slave receiver which is addressed must generate

an acknowledge after the reception of each byte.

IR7, IR3: instruction 7th, 3rd bit.

AC3: address counter 3rd bit.

D7, D3: data 7th, 3rd bit.

Fig 23. Example of 4-bit data transfer timing sequence

mga805

internal

DB7

R/W

internal operation

IR7

IR3

AC3

not

busy

AC3

busy

instruction

write

busy flag

check

busy flag

check

instruction

write

Fig 24. Example of busy ﬂag checking timing sequence

mga806

instruction

write

busy flag

check

busy flag

check

busy flag

check

instruction

write

internal operation

internal

DB7

R/W

data

busy

not

busy

data

PCF2113AU/10/F4 데이터시트(PDF) 37 Page - NXP Semiconductors

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