PCF8564AUSLASH10AASLASH1 datasheet(8/44 Pages) NXP

8 / 44 page

PCF8564A_1

Product data sheet

Rev. 1 — 8 October 2009

8 of 44

NXP Semiconductors

PCF8564A

Real time clock and calendar

8.3.2.1

Interrupt output

Bits TF and AF: When an alarm occurs, AF is set to 1. Similarly, at the end of a timer

countdown, TF is set to 1. These bits maintain their value until overwritten using the

interface. If both timer and alarm interrupts are required in the application, the source of

the interrupt can be determined by reading these bits. To prevent one ﬂag being

overwritten while clearing another, a logic AND is performed during a write access.

Bits TIE and AIE: These bits activate or deactivate the generation of an interrupt when

TF or AF is asserted respectively. The interrupt is the logical OR of these two conditions

when both AIE and TIE are set.

Countdown timer interrupts: The pulse generator for the countdown timer interrupt

uses an internal clock and is dependent on the selected source clock for the countdown

timer and on the countdown value n. As a consequence, the width of the interrupt pulse

varies (see Table 7).

[1]

TF and INT become active simultaneously.

[2]

n = loaded countdown value. Timer is stopped when n = 0.

When bits TIE and AIE are disabled, pin INT will remain high-impedance.

Fig 4.

Interrupt scheme

013aaa087

COUNTDOWN COUNTER

AF: ALARM

FLAG

CLEAR

SET

to interface:

read AF

TF: TIMER

CLEAR

SET

PULSE

GENERATOR 2

CLEAR

TRIGGER

TIE

INT

from interface:

clear TF

from interface:

clear AF

set alarm

flag, AF

to interface:

read TF

TI_TP

AIE

E.G.AIE

Table 7.

INT operation (bit TI_TP = 1)[1]

Source clock (Hz)

INT period (s)

n = 1[2]

n > 1

4096

⁄8192

⁄4096

⁄128

⁄64

⁄60

⁄64

PCF8564AU/10AA/1 데이터시트(PDF) 8 Page - NXP Semiconductors

PCF8564AU/10AA/1 데이터시트(HTML) 8 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

데이터시트 다운로드

링크 URL