PCF85133USLASH2DASLASH1 datasheet(18/41 Pages) NXP

18 / 41 page

PCF85133_1

Product data sheet

Rev. 1 — 17 February 2009

18 of 41

NXP Semiconductors

PCF85133

Universal LCD driver for low multiplex rates

7.16.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as a control signal (see Figure 11).

7.16.1.1

START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy.

A HIGH-to-LOW change of the data line, while the clock is HIGH is deﬁned as the START

condition (S).

A LOW-to-HIGH change of the data line while the clock is HIGH is deﬁned as the STOP

condition (P).

The START and STOP conditions are shown in Figure 12.

7.16.2 System conﬁguration

A device generating a message is a transmitter, a device receiving a message is the

receiver. The device that controls the message is the master and the devices which are

controlled by the master are the slaves. The system conﬁguration is shown in Figure 13.

Fig 11. Bit transfer

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 12. Deﬁnition of START and STOP conditions

mbc622

SDA

SCL

STOP condition

SDA

SCL

START condition

Fig 13. System conﬁguration

mga807

SDA

SCL

MASTER

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

SLAVE

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

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