PCF85133USLASH2DASLASH1 datasheet(20/41 Pages) NXP

20 / 41 page

PCF85133_1

Product data sheet

Rev. 1 — 17 February 2009

20 of 41

NXP Semiconductors

PCF85133

Universal LCD driver for low multiplex rates

7.16.5 Input ﬁlters

To enhance noise immunity in electrically adverse environments, RC low-pass ﬁlters are

provided on the SDA and SCL lines.

7.16.6 I2C-bus protocol

Two I2C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCF85133.

The least signiﬁcant bit of the slave address is bit R/W. The PCF85133 is a write-only

device and will not respond to a read access, so this bit should always be logic 0. The

second bit of the slave address is deﬁned by the level tied at input SA0. Two types of

PCF85133 can be distinguished on the same I2C-bus which allows:

• Up to 16 PCF85133s on the same I2C-bus for very large LCD applications

• The use of two types of LCD multiplex on the same I2C-bus

The I2C-bus protocol is shown in Figure 15. The sequence is initiated with a START

condition (S) from the I2C-bus master which is followed by one of two possible PCF85133

slave addresses available. All PCF85133s with the corresponding SA0 level acknowledge

in parallel to the slave address, but all PCF85133 with the alternative SA0 level ignore the

whole I2C-bus transfer.

After acknowledgement, a control byte follows which deﬁnes if the next byte is RAM or

command information. The control byte also deﬁnes if the next byte is a control byte or

further RAM or command data.

In this way it is possible to conﬁgure the device and then ﬁll the display RAM with little

overhead.

The command bytes and control bytes are also acknowledged by all addressed

PCF85133s connected to the bus.

The display bytes are stored in the display RAM at the address speciﬁed by the data

pointer and the subaddress counter; see Section 7.11 and Section 7.12.

The acknowledgement after each byte is made only by the (A0, A1 and A2) addressed

PCF85133. After the last (display) byte, the I2C-bus master issues a STOP condition (P).

Alternatively a START may be asserted to RESTART an I2C-bus access.

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