PIC16F688-ISLASHML datasheet(64/204 Pages) MICROCHIP

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PIC16F688

DS41203E-page 62

7.8

Comparator C2 Gating Timer1

This feature can be used to time the duration or interval

of analog events. Clearing the T1GSS bit of the

CMCON1 register will enable Timer1 to increment

based on the output of Comparator C2. This requires

that Timer1 is on and gating is enabled. See

Section 6.0 “Timer1 Module with Gate Control” for

details.

It is recommended to synchronize Comparator C2 with

Timer1 by setting the C2SYNC bit when the comparator

is used as the Timer1 gate source. This ensures Timer1

does not miss an increment if the comparator changes

during an increment.

7.9

Synchronizing Comparator C2

Output to Timer1

The output of Comparator C2 can be synchronized with

Timer1 by setting the C2SYNC bit of the CMCON1

latched on the falling edge of the Timer1 clock source.

If a prescaler is used with Timer1, the comparator

output is latched after the prescaling function. To

prevent a race condition, the comparator output is

latched on the falling edge of the Timer1 clock source

and Timer1 increments on the rising edge of its clock

source. Reference the comparator block diagrams

(Figure 7-2 and Figure 7-3) and the Timer1 Block

Diagram (Figure 6-1) for more information.

CMCON1: COMPARATOR CONFIGURATION REGISTER

U-0

R/W-1

R/W-0

—

T1GSS

C2SYNC

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-2

Unimplemented: Read as ‘0’

bit 1

T1GSS: Timer1 Gate Source Select bit(1)

= Timer1 gate source is T1G pin (pin should be configured as digital input)

= Timer1 gate source is Comparator C2 output

bit 0

C2SYNC: Comparator C2 Output Synchronization bit(2)

= Output is synchronized with falling edge of Timer1 clock

= Output is asynchronous

Note 1:

Refer to Section 6.6 “Timer1 Gate”.

Refer to Figure 7-3.

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