PIC16F688-ISLASHML datasheet(69/204 Pages) MICROCHIP

69 / 204 page

DS41203E-page 67

PIC16F688

TABLE 8-1:

ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V)

FIGURE 8-2:

ANALOG-TO-DIGITAL CONVERSION TAD CYCLES

ADC Clock Period (TAD)

Device Frequency (FOSC)

ADC Clock Source

ADCS<2:0>

20 MHz

8 MHz

4 MHz

1 MHz

FOSC/2

000

100 ns(2)

250 ns(2)

500 ns(2)

2.0

μs

FOSC/4

100

200 ns(2)

500 ns(2)

1.0

μs(2)

4.0

μs

FOSC/8

001

400 ns(2)

1.0

μs(2)

2.0

μs

8.0

μs(3)

FOSC/16

101

800 ns(2)

2.0

μs4.0 μs

16.0

μs(3)

FOSC/32

010

1.6

μs4.0 μs

8.0

μs(3)

32.0

μs(3)

FOSC/64

110

3.2

μs

8.0

μs(3)

16.0

μs(3)

64.0

μs(3)

FRC

x11

2-6

μs(1,4)

2-6

μs(1,4)

2-6

μs(1,4)

2-6

μs(1,4)

Legend: Shaded cells are outside of recommended range.

Note 1:

The FRC source has a typical TAD time of 4

μs for VDD > 3.0V.

These values violate the minimum required TAD time.

For faster conversion times, the selection of another clock source is recommended.

When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the

conversion will be performed during Sleep.

TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9

Set GO/DONE bit

Holding Capacitor is Disconnected from Analog Input (typically 100 ns)

TAD10 TAD11

TCY to TAD

Conversion Starts

ADRESH and ADRESL registers are loaded,

GO bit is cleared,

ADIF bit is set,

Holding capacitor is connected to analog input

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