PIC16F690-ESLASHML datasheet(44/306 Pages) MICROCHIP

44 / 306 page

PIC16F631/677/685/687/689/690

DS41262E-page 42

2.2.2.7

PIR2 Register

The PIR2 register contains the interrupt flag bits, as

shown in Register 2-7.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE of the INTCON register.

User

software

should

ensure

the

appropriate interrupt flag bits are clear prior

to enabling an interrupt.

PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2

R/W-0

U-0

OSFIF

C2IF

C1IF

EEIF

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

OSFIF: Oscillator Fail Interrupt Flag bit

= System oscillator failed, clock input has changed to INTOSC (must be cleared in software)

= System clock operating

bit 6

C2IF: Comparator C2 Interrupt Flag bit

= Comparator output (C2OUT bit) has changed (must be cleared in software)

= Comparator output (C2OUT bit) has not changed

bit 5

C1IF: Comparator C1 Interrupt Flag bit

= Comparator output (C1OUT bit) has changed (must be cleared in software)

= Comparator output (C1OUT bit) has not changed

bit 4

EEIF: EE Write Operation Interrupt Flag bit

= Write operation completed (must be cleared in software)

= Write operation has not completed or has not started

bit 3-0

Unimplemented: Read as ‘0’

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