12C508 datasheet(34/113 Pages) MICROCHIP

34 / 113 page

PIC12C5XX

DS40139E-page 34

7.5

READ OPERATIONS

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

slave address is set to one. There are three basic types

of read operations: current address read, random read,

and sequential read.

7.5.1

CURRENT ADDRESS READ

It contains an address counter that maintains the

address of the last word accessed, internally incre-

mented by one. Therefore, if the previous read access

was to address n, the next current address read opera-

tion would access data from address n + 1. Upon

receipt of the slave address with the R/W bit set to one,

the device issues an acknowledge and transmits the

eight bit data word. The master will not acknowledge

the transfer but does generate a stop condition and the

device discontinues transmission (Figure 7-8).

7.5.2

RANDOM READ

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, first the word address must

be set. This is done by sending the word address to the

device as part of a write operation. After the word

address is sent, the master generates a start condition

following the acknowledge. This terminates the write

operation, but not before the internal address pointer is

set. Then the master issues the control byte again but

with the R/W bit set to a one. It will then issue an

acknowledge and transmits the eight bit data word. The

master will not acknowledge the transfer but does gen-

erate a stop condition and the device discontinues

transmission (Figure 7-9). After this command, the

internal address counter will point to the address loca-

tion following the one that was just read.

7.5.3

SEQUENTIAL READ

Sequential reads are initiated in the same way as a ran-

dom read except that after the device transmits the first

data byte, the master issues an acknowledge as

opposed to a stop condition in a random read. This

directs the device to transmit the next sequentially

addressed 8-bit word (Figure 7-10).

To provide sequential reads, it contains an internal

address pointer which is incremented by one at the

completion of each read operation. This address

pointer allows the entire memory contents to be serially

read during one operation.

FIGURE 7-8:

CURRENT ADDRESS READ

FIGURE 7-9:

RANDOM READ

FIGURE 7-10: SEQUENTIAL READ

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

DATA

00 X X X 1

X = Don’t Care Bit

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

WORD

ADDRESS (n)

CONTROL

BYTE

DATA (n)

X XXX

00 X X X 0

S 1

00 X X X 1

X = Don’t Care Bit

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

DATA n

DATA n + 1

DATA n + 2

DATA n + X

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