MPC8308CVMADDA datasheet(82/88 Pages) FREESCALE

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MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1

Freescale Semiconductor

System Design Information

23.1

System Clocking

The device includes two PLLs.

1. The platform PLL generates the platform clock from the externally supplied SYS_CLK_IN input.

The frequency ratio between the platform and SYS_CLK_IN is selected using the platform PLL

ratio configuration bits as described in Section 21.2, “System PLL Configuration.”

2. The e300 core PLL generates the core clock as a slave to the platform clock. The frequency ratio

between the e300 core clock and the platform clock is selected using the e300 PLL ratio

configuration bits as described in Section 21.3, “Core PLL Configuration.”

23.2

PLL Power Supply Filtering

Each of the PLLs listed above is provided with power through independent power supply pins (AVDD1 for

core PLL and AVDD2 for the platform PLL). The AVDD level should always be equivalent to VDD, and

preferably these voltages are derived directly from VDD through a low-pass filter scheme such as the

following.

There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to

provide independent filter circuits as illustrated in Figure 54, one to each of the two AVDD pins. By

providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the

other is reduced.

This circuit is intended to filter noise in the PLLs’ resonant frequency range from a 500 kHz to 10 MHz

range. It should be built with surface mount capacitors with minimum effective series inductance (ESL).

Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook

of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a

single large value capacitor.

Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize

noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD

pin, which is on the periphery of package, without the inductance of vias.

Figure 54 shows the PLL power supply filter circuits.

Figure 54. PLL Power Supply Filter Circuit

23.3

Decoupling Recommendations

Due to large address and data buses and high-operating frequencies, the device can generate transient

power surges and high-frequency noise in its power supply, especially while driving large capacitive loads.

This noise must be prevented from reaching other components in the MPC8308 system, and the MPC8308

itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system

designer place at least one decoupling capacitor at each VDD, NVDD, GVDD, and LVDD pin of the device.

VDD

AVDD1 and AVDD2

2.2 µF

Low ESL Surface Mount Capacitors

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