CAT310

http://onsemi.com

7

TYPICAL CHARACTERISTICS

Figure 9. Output Channel Leakage vs. Bias

Voltage

Figure 10. Quiescent Current vs. Temperature

OUTPUT PIN BIAS VOLTAGE (V)

TEMPERATURE (°C)

15

14

13

16

12

11

10

0

2

4

6

8

10

12

14

100

75

125

50

25

0

−25

−50

0

5

10

15

20

Figure 11. VBATT Overvoltage Detection vs.

Temperature

Figure 12. VCC Undervoltage Lockout vs.

Temperature

TEMPERATURE (°C)

TEMPERATURE (°C)

100

75

50

125

25

0

−25

−50

14

16

18

20

22

24

100

75

125

50

25

0

−25

−50

0

0.5

1.0

1.5

2.0

2.5

3.0

125°C

−40°C

85°C

25°C

Functional Description

The CAT310 implements a 10−bit serial−in shift register

for storing the setting of the ten outputs. Serial input data

SIN are clocked into the shift register on the rising edge of

is outputted from the shift register to SOUT. The following

clock pulses will output the following data bits onto SOUT.

The output data pattern replicates the input data stream with

a delay of ten clock pulses.

The 10−bit data pattern present in the shift register is

stored in the 10−bit data latch when the latch signal XLAT

is logic high. When XLAT transitions to logic low, data are

latched and stay unchanged for as long as XLAT remains

low. The last serial input data corresponds to OUT0. The

serial input data that was received 10 clock pulse ago is

stored in OUT9. When the BLANK input is logic high, all

the output switches are in the off state. If the BLANK input

is low, the 10−bit data latches control the 10 output switches.

A data bit value of zero keeps the switch off. A data bit value

of one keeps the switch on.

Serial to Parallel Shift Register

CLK →

SIN →

Bit

0

Bit

1

Bit

2

Bit

3

Bit

4

Bit

5

Bit

6

Bit

7

Bit

8

Bit

9

→ SOUT

Data Latch

↓

↓

↓

↓

↓

↓

↓

↓

↓

↓

XLAT →

LED

OUT0

LED

OUT1

LED

OUT2

LED

OUT3

LED

OUT4

LED

OUT5

LED

OUT6

LED

OUT7

LED

OUT8

LED

OUT9