M24C16-RBN3TPSLASHS datasheet(14/39 Pages) STMICROELECTRONICS

14 / 39 page

Device operation

M24C16, M24C08, M24C04, M24C02, M24C01

14/39

Doc ID 5067 Rev 16

the addressed location is not Write-protected, the device replies with Ack. The bus master

terminates the transfer by generating a Stop condition, as shown in Figure 8.

3.6.2

Page Write

The Page Write mode allows up to 16 bytes to be written in a single Write cycle, provided

that they are all located in the same page in the memory: that is, the most significant

memory address bits are the same. If more bytes are sent than will fit up to the end of the

page, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to

become overwritten in an implementation dependent way.

The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the

device if Write Control (WC) is Low. If the addressed location is Write-protected, by Write

Control (WC) being driven High (during the period from the Start condition until the end of

the address byte), the device replies to the data bytes with NoAck, as shown in Figure 7,

and the locations are not modified. After each byte is transferred, the internal byte address

counter (the 4 least significant address bits only) is incremented. The transfer is terminated

by the bus master generating a Stop condition.

Figure 8.

Write mode sequences with WC = 0 (data write enabled)

Byte Write

Dev Select

Byte address

Data in

Page Write

Dev Select

Byte address

Data in 1

Data in 2

Data in 3

AI02804c

Page Write

(cont'd)

WC (cont'd)

Data in N

ACK

R/W

ACK

R/W

ACK

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