PC912XDP512F0MPVR datasheet(328/1348 Pages) FREESCALE

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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

328

Freescale Semiconductor

7.3.2.12

Main Timer Interrupt Flag 1 (TFLG1)

Read: Anytime

Write used in the ﬂag clearing mechanism. Writing a one to the ﬂag clears the ﬂag. Writing a zero will not

affect the current status of the bit.

NOTE

When TFFCA = 1, the ﬂags cannot be cleared via the normal ﬂag clearing

mechanism (writing a one to the ﬂag). Reference Section 7.3.2.6, “Timer

System Control Register 1 (TSCR1)”.

All bits reset to zero.

TFLG1 indicates when interrupt conditions have occurred. The ﬂags can be cleared via the normal ﬂag

clearing mechanism (writing a one to the ﬂag) or via the fast ﬂag clearing mechanism (reference TFFCA

bit in Section 7.3.2.6, “Timer System Control Register 1 (TSCR1)”).

Use of the TFMOD bit in the ICSYS register in conjunction with the use of the ICOVW register allows a

timer interrupt to be generated after capturing two values in the capture and holding registers, instead of

generating an interrupt for every capture.

76543210

C7F

C6F

C5F

C4F

C3F

C2F

C1F

C0F

Reset

00000000

Figure 7-17. Main Timer Interrupt Flag 1 (TFLG1)

Table 7-16. TFLG1 Field Descriptions

Field

Description

7:0

C[7:0]F

Input Capture/Output Compare Channel “x” Flag — A CxF ﬂag is set when a corresponding input capture or

output compare is detected. C0F can also be set by 16-bit Pulse Accumulator B (PACB). C3F–C0F can also be

set by 8-bit pulse accumulators PAC3–PAC0.

If the delay counter is enabled, the CxF ﬂag will not be set until after the delay.

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