PC912XDP512F0MPVR datasheet(332/1348 Pages) FREESCALE

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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

332

Freescale Semiconductor

Read: Anytime

Write anytime for output compare function. Writes to these registers have no meaning or effect during

input capture.

All bits reset to zero.

Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the

free-running counter when a deﬁned transition is sensed by the corresponding input capture edge detector

or to trigger an output action for output compare.

7.3.2.15

16-Bit Pulse Accumulator A Control Register (PACTL)

Read: Anytime

Write: Anytime

All bits reset to zero.

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Reset

00000000

Figure 7-33. Timer Input Capture/Output Compare Register 7 High (TC7)

76543210

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

00000000

Figure 7-34. Timer Input Capture/Output Compare Register 7 Low (TC7)

76543210

PAEN

PAMOD

PEDGE

CLK1

CLK0

PAOVI

PAI

Reset

00000000

= Unimplemented or Reserved

Figure 7-35. 16-Bit Pulse Accumulator Control Register (PACTL)

Table 7-18. PACTL Field Descriptions

Field

Description

PAEN

Pulse Accumulator A System Enable — PAEN is independent from TEN. With timer disabled, the pulse

accumulator can still function unless pulse accumulator is disabled.

0 16-Bit Pulse Accumulator A system disabled. 8-bit PAC3 and PAC2 can be enabled when their related enable

bits in ICPAR are set. Pulse Accumulator Input Edge Flag (PAIF) function is disabled.

1 16-Bit Pulse Accumulator A system enabled. The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded

to form the PACA 16-bit pulse accumulator. When PACA in enabled, the PACN3 and PACN2 registers contents

are respectively the high and low byte of the PACA. PA3EN and PA2EN control bits in ICPAR have no effect.

Pulse Accumulator Input Edge Flag (PAIF) function is enabled. The PACA shares the input pin with IC7.

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