PC912XDP512F0MPVR datasheet(337/1348 Pages) FREESCALE

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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

337

7.3.2.19

16-Bit Modulus Down-Counter Control Register (MCCTL)

Read: Anytime

Write: Anytime

All bits reset to zero.

76543210

MCZI

MODMC

RDMCL

MCEN

MCPR1

MCPR0

ICLAT

FLMC

Reset

00000000

Figure 7-41. 16-Bit Modulus Down-Counter Control Register (MCCTL)

Table 7-22. MCCTL Field Descriptions

Field

Description

MCZI

Modulus Counter Underﬂow Interrupt Enable

0 Modulus counter interrupt is disabled.

1 Modulus counter interrupt is enabled.

MODMC

Modulus Mode Enable

0 The modulus counter counts down from the value written to it and will stop at 0x0000.

1 Modulus mode is enabled. When the modulus counter reaches 0x0000, the counter is loaded with the latest

value written to the modulus count register.

Note: For proper operation, the MCEN bit should be cleared before modifying the MODMC bit in order to reset

the modulus counter to 0xFFFF.

RDMCL

Read Modulus Down-Counter Load

0 Reads of the modulus count register (MCCNT) will return the present value of the count register.

1 Reads of the modulus count register (MCCNT) will return the contents of the load register.

ICLAT

Input Capture Force Latch Action — When input capture latch mode is enabled (LATQ and BUFEN bit in

ICSYS are set), a write one to this bit immediately forces the contents of the input capture registers TC0 to TC3

and their corresponding 8-bit pulse accumulators to be latched into the associated holding registers. The pulse

accumulators will be automatically cleared when the latch action occurs.

Writing zero to this bit has no effect. Read of this bit will always return zero.

FLMC

Force Load Register into the Modulus Counter Count Register — This bit is active only when the modulus

down-counter is enabled (MCEN = 1).

A write one into this bit loads the load register into the modulus counter count register (MCCNT). This also resets

the modulus counter prescaler.

Write zero to this bit has no effect. Read of this bit will return always zero.

MCEN

Modulus Down-Counter Enable

0 Modulus counter disabled. The modulus counter (MCCNT) is preset to 0xFFFF. This will prevent an early

interrupt ﬂag when the modulus down-counter is enabled.

1 Modulus counter is enabled.

1:0

MCPR[1:0]

Modulus Counter Prescaler Select — These two bits specify the division rate of the modulus counter prescaler

when PRNT of TSCR1 is set to 0. The newly selected prescaler division rate will not be effective until a load of

the load register into the modulus counter count register occurs.

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