PC912XDP512F0MPVR datasheet(338/1348 Pages) FREESCALE

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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

338

Freescale Semiconductor

7.3.2.20

16-Bit Modulus Down-Counter FLAG Register (MCFLG)

Read: Anytime

Write only used in the ﬂag clearing mechanism for bit 7. Writing a one to bit 7 clears the ﬂag. Writing a

zero will not affect the current status of the bit.

NOTE

When TFFCA = 1, the ﬂag cannot be cleared via the normal ﬂag clearing

mechanism (writing a one to the ﬂag). Reference Section 7.3.2.6, “Timer

System Control Register 1 (TSCR1)”.

All bits reset to zero.

Table 7-23. Modulus Counter Prescaler Select

MCPR1

MCPR0

Prescaler Division

76543210

MCZF

POLF3

POLF2

POLF1

POLF0

Reset

00000000

= Unimplemented or Reserved

Figure 7-42. 16-Bit Modulus Down-Counter FLAG Register (MCFLG)

Table 7-24. MCFLG Field Descriptions

Field

Description

MCZF

Modulus Counter Underﬂow Flag — The ﬂag is set when the modulus down-counter reaches 0x0000.

The ﬂag indicates when interrupt conditions have occurred. The ﬂag can be cleared via the normal ﬂag clearing

mechanism (writing a one to the ﬂag) or via the fast ﬂag clearing mechanism (Reference TFFCA bit in

Section 7.3.2.6, “Timer System Control Register 1 (TSCR1)”).

3:0

POLF[3:0]

First Input Capture Polarity Status — These are read only bits. Writes to these bits have no effect.

Each status bit gives the polarity of the ﬁrst edge which has caused an input capture to occur after capture latch

has been read.

Each POLFx corresponds to a timer PORTx input.

0 The ﬁrst input capture has been caused by a falling edge.

1 The ﬁrst input capture has been caused by a rising edge.

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