PC912XDP512F0MPVR datasheet(472/1348 Pages) FREESCALE

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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)

MC9S12XDP512 Data Sheet, Rev. 2.21

472

Freescale Semiconductor

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CPU is in wait mode and the CSWAI bit is set

When entering the power down mode, the MSCAN immediately stops all ongoing transmissions and

receptions, potentially causing CAN protocol violations. To protect the CAN bus system from fatal

consequences of violations to the above rule, the MSCAN immediately drives the TXCAN pin into a

recessive state.

NOTE

The user is responsible for ensuring that the MSCAN is not active when

power down mode is entered. The recommended procedure is to bring the

MSCAN into Sleep mode before the STOP or WAI instruction (if CSWAI

is set) is executed. Otherwise, the abort of an ongoing message can cause an

error condition and impact other CAN bus devices.

In power down mode, all clocks are stopped and no registers can be accessed. If the MSCAN was not in

sleep mode before power down mode became active, the module performs an internal recovery cycle after

powering up. This causes some ﬁxed delay before the module enters normal mode again.

10.4.5.7

Programmable Wake-Up Function

The MSCAN can be programmed to wake up the MSCAN as soon as CAN bus activity is detected (see

control bit WUPE in Section 10.3.2.1, “MSCAN Control Register 0 (CANCTL0)”). The sensitivity to

existing CAN bus action can be modiﬁed by applying a low-pass ﬁlter function to the RXCAN input line

while in sleep mode (see control bit WUPM in Section 10.3.2.2, “MSCAN Control Register 1

(CANCTL1)”).

This feature can be used to protect the MSCAN from wake-up due to short glitches on the CAN bus lines.

Such glitches can result from—for example—electromagnetic interference within noisy environments.

10.4.6

Reset Initialization

The reset state of each individual bit is listed in Section 10.3.2, “Register Descriptions,” which details all

the registers and their bit-ﬁelds.

10.4.7

Interrupts

This section describes all interrupts originated by the MSCAN. It documents the enable bits and generated

ﬂags. Each interrupt is listed and described separately.

10.4.7.1

Description of Interrupt Operation

The MSCAN supports four interrupt vectors (see Table 10-37), any of which can be individually masked

(for details see sections from Section 10.3.2.6, “MSCAN Receiver Interrupt Enable Register

(CANRIER),” to Section 10.3.2.8, “MSCAN Transmitter Interrupt Enable Register (CANTIER)”).

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