PC912XDP512F0MPVR datasheet(513/1348 Pages) FREESCALE

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Chapter 11 Serial Communication Interface (S12SCIV5)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

513

11.5.3.1

Description of Interrupt Operation

The SCI only originates interrupt requests. The following is a description of how the SCI makes a request

and how the MCU should acknowledge that request. The interrupt vector offset and interrupt number are

chip dependent. The SCI only has a single interrupt line (SCI Interrupt Signal, active high operation) and

all the following interrupts, when generated, are ORed together and issued through that port.

11.5.3.1.1

TDRE Description

The TDRE interrupt is set high by the SCI when the transmit shift register receives a byte from the SCI

data register. A TDRE interrupt indicates that the transmit data register (SCIDRH/L) is empty and that a

new byte can be written to the SCIDRH/L for transmission.Clear TDRE by reading SCI status register 1

with TDRE set and then writing to SCI data register low (SCIDRL).

11.5.3.1.2

TC Description

The TC interrupt is set by the SCI when a transmission has been completed. Transmission is completed

when all bits including the stop bit (if transmitted) have been shifted out and no data is queued to be

transmitted. No stop bit is transmitted when sending a break character and the TC ﬂag is set (providing

there is no more data queued for transmission) when the break character has been shifted out. A TC

interrupt indicates that there is no transmission in progress. TC is set high when the TDRE ﬂag is set and

no data, preamble, or break character is being transmitted. When TC is set, the TXD pin becomes idle

(logic 1). Clear TC by reading SCI status register 1 (SCISR1) with TC set and then writing to SCI data

be sent.

11.5.3.1.3

RDRF Description

The RDRF interrupt is set when the data in the receive shift register transfers to the SCI data register. A

RDRF interrupt indicates that the received data has been transferred to the SCI data register and that the

byte can now be read by the MCU. The RDRF interrupt is cleared by reading the SCI status register one

(SCISR1) and then reading SCI data register low (SCIDRL).

11.5.3.1.4

OR Description

The OR interrupt is set when software fails to read the SCI data register before the receive shift register

receives the next frame. The newly acquired data in the shift register will be lost in this case, but the data

already in the SCI data registers is not affected. The OR interrupt is cleared by reading the SCI status

11.5.3.1.5

IDLE Description

The IDLE interrupt is set when 10 consecutive logic 1s (if M = 0) or 11 consecutive logic 1s (if M = 1)

appear on the receiver input. Once the IDLE is cleared, a valid frame must again set the RDRF ﬂag before

an idle condition can set the IDLE ﬂag. Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE

set and then reading SCI data register low (SCIDRL).

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