PC912XDP512F0MPVR datasheet(521/1348 Pages) FREESCALE

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Chapter 12 Serial Peripheral Interface (S12SPIV4)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

521

12.3.2.2

SPI Control Register 2 (SPICR2)

Read: Anytime

Write: Anytime; writes to the reserved bits have no effect

Table 12-2. SS Input / Output Selection

MODFEN

SSOE

Master Mode

Slave Mode

SS not used by SPI

SS input

SS not used by SPI

SS input

SS input with MODF feature

SS input

SS is slave select output

SS input

76543210

000

MODFEN

BIDIROE

SPISWAI

SPC0

Reset

00000000

= Unimplemented or Reserved

Figure 12-4. SPI Control Register 2 (SPICR2)

Table 12-3. SPICR2 Field Descriptions

Field

Description

MODFEN

Mode Fault Enable Bit — This bit allows the MODF failure to be detected. If the SPI is in master mode and

MODFEN is cleared, then the SS port pin is not used by the SPI. In slave mode, the SS is available only as an

input regardless of the value of MODFEN. For an overview on the impact of the MODFEN bit on the SS port pin

conﬁguration, refer to Table 12-4. In master mode, a change of this bit will abort a transmission in progress and

force the SPI system into idle state.

0 SS port pin is not used by the SPI.

1 SS port pin with MODF feature.

BIDIROE

Output Enable in the Bidirectional Mode of Operation — This bit controls the MOSI and MISO output buffer

of the SPI, when in bidirectional mode of operation (SPC0 is set). In master mode, this bit controls the output

buffer of the MOSI port, in slave mode it controls the output buffer of the MISO port. In master mode, with SPC0

set, a change of this bit will abort a transmission in progress and force the SPI into idle state.

0 Output buffer disabled.

1 Output buffer enabled.

SPISWAI

SPI Stop in Wait Mode Bit — This bit is used for power conservation while in wait mode.

0 SPI clock operates normally in wait mode.

1 Stop SPI clock generation when in wait mode.

SPC0

Serial Pin Control Bit 0 — This bit enables bidirectional pin conﬁgurations as shown in Table 12-4. In master

mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state.

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