PC912XDP512F0MPVR datasheet(530/1348 Pages) FREESCALE

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Chapter 12 Serial Peripheral Interface (S12SPIV4)

MC9S12XDP512 Data Sheet, Rev. 2.21

530

Freescale Semiconductor

12.4.2

Slave Mode

The SPI operates in slave mode when the MSTR bit in SPI control register 1 is clear.

•

Serial clock

In slave mode, SCK is the SPI clock input from the master.

•

MISO, MOSI pin

In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI)

is determined by the SPC0 bit and BIDIROE bit in SPI control register 2.

•

SS pin

The SS pin is the slave select input. Before a data transmission occurs, the SS pin of the slave SPI

must be low. SS must remain low until the transmission is complete. If SS goes high, the SPI is

forced into idle state.

The SS input also controls the serial data output pin, if SS is high (not selected), the serial data

output pin is high impedance, and, if SS is low, the ﬁrst bit in the SPI data register is driven out of

the serial data output pin. Also, if the slave is not selected (SS is high), then the SCK input is

ignored and no internal shifting of the SPI shift register occurs.

Although the SPI is capable of duplex operation, some SPI peripherals are capable of only

receiving SPI data in a slave mode. For these simpler devices, there is no serial data out pin.

NOTE

When peripherals with duplex capability are used, take care not to

simultaneously enable two receivers whose serial outputs drive the same

system slave’s serial data output line.

As long as no more than one slave device drives the system slave’s serial data output line, it is possible for

several slaves to receive the same transmission from a master, although the master would not receive return

information from all of the receiving slaves.

If the CPHA bit in SPI control register 1 is clear, odd numbered edges on the SCK input cause the data at

the serial data input pin to be latched. Even numbered edges cause the value previously latched from the

serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit.

If the CPHA bit is set, even numbered edges on the SCK input cause the data at the serial data input pin to

be latched. Odd numbered edges cause the value previously latched from the serial data input pin to shift

into the LSB or MSB of the SPI shift register, depending on the LSBFE bit.

When CPHA is set, the ﬁrst edge is used to get the ﬁrst data bit onto the serial data output pin. When CPHA

is clear and the SS input is low (slave selected), the ﬁrst bit of the SPI data is driven out of the serial data

output pin. After the eighth shift, the transfer is considered complete and the received data is transferred

into the SPI data register. To indicate transfer is complete, the SPIF ﬂag in the SPI status register is set.

NOTE

A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0, or

BIDIROE with SPC0 set in slave mode will corrupt a transmission in

progress and must be avoided.

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