PC912XDP512F0MPVR datasheet(533/1348 Pages) FREESCALE

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Chapter 12 Serial Peripheral Interface (S12SPIV4)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

533

In slave mode, if the SS line is not deasserted between the successive transmissions then the content of the

SPI data register is not transmitted; instead the last received byte is transmitted. If the SS line is deasserted

for at least minimum idle time (half SCK cycle) between successive transmissions, then the content of the

SPI data register is transmitted.

In master mode, with slave select output enabled the SS line is always deasserted and reasserted between

successive transfers for at least minimum idle time.

12.4.3.3

CPHA = 1 Transfer Format

Some peripherals require the ﬁrst SCK edge before the ﬁrst data bit becomes available at the data out pin,

the second edge clocks data into the system. In this format, the ﬁrst SCK edge is issued by setting the

CPHA bit at the beginning of the 8-cycle transfer operation.

The ﬁrst edge of SCK occurs immediately after the half SCK clock cycle synchronization delay. This ﬁrst

edge commands the slave to transfer its ﬁrst data bit to the serial data input pin of the master.

A half SCK cycle later, the second edge appears on the SCK pin. This is the latching edge for both the

master and slave.

When the third edge occurs, the value previously latched from the serial data input pin is shifted into the

LSB or MSB of the SPI shift register, depending on LSBFE bit. After this edge, the next bit of the master

data is coupled out of the serial data output pin of the master to the serial input pin on the slave.

This process continues for a total of 16 edges on the SCK line with data being latched on even numbered

edges and shifting taking place on odd numbered edges.

Data reception is double buffered, data is serially shifted into the SPI shift register during the transfer and

is transferred to the parallel SPI data register after the last bit is shifted in.

After the 16th SCK edge:

•

Data that was previously in the SPI data register of the master is now in the data register of the

slave, and data that was in the data register of the slave is in the master.

•

The SPIF ﬂag bit in SPISR is set indicating that the transfer is complete.

Figure 12-12 shows two clocking variations for CPHA = 1. The diagram may be interpreted as a master or

slave timing diagram because the SCK, MISO, and MOSI pins are connected directly between the master

and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the

master. The SS line is the slave select input to the slave. The SS pin of the master must be either high or

reconﬁgured as a general-purpose output not affecting the SPI.

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